/*
 * Copyright (C) 2019 Unigroup Spreadtrum & RDA Technologies Co., Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2019-02-11 15:07:05
 *
 */


#ifndef ANLG_PHY_G0_H
#define ANLG_PHY_G0_H

#define CTL_BASE_ANLG_PHY_G0 0x63470000


#define REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL0   ( CTL_BASE_ANLG_PHY_G0 + 0x0000 )
#define REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL1   ( CTL_BASE_ANLG_PHY_G0 + 0x0004 )
#define REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL2   ( CTL_BASE_ANLG_PHY_G0 + 0x0008 )
#define REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL3   ( CTL_BASE_ANLG_PHY_G0 + 0x000C )
#define REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL4   ( CTL_BASE_ANLG_PHY_G0 + 0x0010 )
#define REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL5   ( CTL_BASE_ANLG_PHY_G0 + 0x0014 )
#define REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL6   ( CTL_BASE_ANLG_PHY_G0 + 0x0018 )
#define REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL7   ( CTL_BASE_ANLG_PHY_G0 + 0x001C )
#define REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL8   ( CTL_BASE_ANLG_PHY_G0 + 0x0020 )
#define REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL9   ( CTL_BASE_ANLG_PHY_G0 + 0x0024 )
#define REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL10  ( CTL_BASE_ANLG_PHY_G0 + 0x0028 )
#define REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL11  ( CTL_BASE_ANLG_PHY_G0 + 0x002C )
#define REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL12  ( CTL_BASE_ANLG_PHY_G0 + 0x0030 )
#define REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL13  ( CTL_BASE_ANLG_PHY_G0 + 0x0034 )
#define REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL14  ( CTL_BASE_ANLG_PHY_G0 + 0x0038 )
#define REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL15  ( CTL_BASE_ANLG_PHY_G0 + 0x003C )
#define REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL16  ( CTL_BASE_ANLG_PHY_G0 + 0x0040 )
#define REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_REG_SEL_CFG_0   ( CTL_BASE_ANLG_PHY_G0 + 0x0044 )

/* REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL0 */

#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_26MHZ_BUF_PD                BIT(23)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_26MHZ_CUR_SEL(x)            (((x) & 0x3) << 21)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CLK26M_RESERVED(x)          (((x) & 0xF) << 17)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_BG_RBIAS_MODE               BIT(16)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TESTMUX(x)                  (((x) & 0xFFFF))

/* REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL1 */

#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_BIST_CTRL(x)           (((x) & 0xFF) << 22)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_BIST_EN                BIT(21)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_CP_EN                  BIT(20)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_CLKOUT_EN              BIT(19)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_DIV_S                  BIT(18)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_CALI_MODE(x)           (((x) & 0x3) << 16)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_CALI_INI(x)            (((x) & 0x1F) << 11)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_CALI_TRIG              BIT(10)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_CALI_WAITCNT(x)        (((x) & 0x3) << 8)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_CALI_POLARITY          BIT(7)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_CALI_DONE              BIT(6)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_CALI_OUT(x)            (((x) & 0x1F) << 1)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_CALI_CPPD              BIT(0)

/* REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL2 */

#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_MOD_EN                 BIT(28)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_NINT(x)                (((x) & 0xFF) << 20)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_KINT(x)                (((x) & 0xFFFFF))

/* REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL3 */

#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_N(x)                   (((x) & 0x7FF) << 13)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_PD                     BIT(12)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_POSTDIV                BIT(11)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_REFCK_SEL(x)           (((x) & 0x3) << 9)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_RST                    BIT(8)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_SDM_EN                 BIT(7)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_CP_OFFSET(x)           (((x) & 0x7) << 4)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_FBDIV_EN               BIT(3)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_ICP(x)                 (((x) & 0x7))

/* REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL4 */

#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_LDO_TRIM(x)            (((x) & 0xF) << 21)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_BIST_CNT(x)            (((x) & 0xFFFF) << 5)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_LOCK_DONE              BIT(4)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_TEST_CLK_EN            BIT(3)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_TEST_CLK_OD            BIT(2)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_TEST_CLK_DIV(x)        (((x) & 0x3))

/* REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL5 */

#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_FREQ_DIFF_EN           BIT(27)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_DIVN(x)                (((x) & 0x1F) << 22)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_PREDIV                 BIT(21)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_R2_SEL(x)              (((x) & 0x7) << 18)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_R3_SEL(x)              (((x) & 0x3) << 16)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_C2_SEL(x)              (((x) & 0x7) << 13)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_KVCO_SEL(x)            (((x) & 0x7) << 10)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_VCO_TEST_EN            BIT(9)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_VCO_TEST_INT           BIT(8)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_VCO_TEST_INTSEL(x)     (((x) & 0x7) << 5)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_SHORT_CSR_EN           BIT(4)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_ALLOP_PD               BIT(3)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_TEST_VCO_PN            BIT(2)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_VCOBUF_EN              BIT(1)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_DOUBLER_EN             BIT(0)

/* REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL6 */

#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CLK_GEN_DIV(x)              (((x) & 0x3F) << 6)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_EN                    BIT(5)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_RSTN                  BIT(4)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_CLK_EN                BIT(3)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_IQ_SWAP               BIT(2)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_ANA_CLK_EDGE_SEL      BIT(1)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_DIG_CLK_EDGE_SEL      BIT(0)

/* REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL7 */

#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_CLK_FQ_SEL(x)         (((x) & 0x3) << 29)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_CAL_EN                BIT(28)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_CAL_RSTN              BIT(27)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_CAL_CLK_FQ_SEL(x)     (((x) & 0x3) << 25)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_CAL_AVG(x)            (((x) & 0x7) << 22)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_CAL_OVWR_EN           BIT(21)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_CAL_OVWR_D(x)         (((x) & 0x7) << 18)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_CAL_READ_EN           BIT(17)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_CAL_DONE              BIT(16)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_OFFSETI(x)            (((x) & 0xFF) << 8)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_OFFSETQ(x)            (((x) & 0xFF))

/* REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL8 */

#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_CUR_SEL(x)            (((x) & 0x3) << 28)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_I2VBUF_OFFSET_CAL_EN  BIT(27)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_I2VBUF_PCAL(x)        (((x) & 0x1F) << 22)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_I2VBUF_NCAL(x)        (((x) & 0x1F) << 17)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_I2VBUF_VCMI_SEL(x)    (((x) & 0x3) << 15)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_I2VBUF_VCMO_SEL(x)    (((x) & 0x3) << 13)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_I2VBUF_GAIN(x)        (((x) & 0xF) << 9)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_I2VBUF_BW_SEL(x)      (((x) & 0x3F) << 3)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_I2VBUF_MODE_SEL       BIT(2)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_I2VBUF_BYPASS         BIT(1)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_I2VBUF_EN             BIT(0)

/* REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL9 */

#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_RESERVED(x)           (((x) & 0x3FF) << 17)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_LDO_1P2_EN            BIT(16)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_LDO_1P2_V(x)          (((x) & 0x7) << 13)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_LDO_0P8_EN            BIT(12)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_TXDAC_LDO_0P8_V(x)          (((x) & 0x7) << 9)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_LDO_EN                  BIT(8)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_EN                      BIT(7)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_RSTN                    BIT(6)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_DIG_EN                  BIT(5)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_CLK_OUT_EN              BIT(4)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_CLK_IN_SEL(x)           (((x) & 0x3) << 2)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_CLK_DIG_EDGE_S          BIT(1)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_CLK_OUT_SEL             BIT(0)

/* REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL10 */

#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_VREF_BST(x)             (((x) & 0x7) << 25)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_VREF_SEL(x)             (((x) & 0x7) << 22)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_CAP_SEL(x)              (((x) & 0x3) << 20)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_BIT_SEL(x)              (((x) & 0x3) << 18)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_MODE_WR                 BIT(17)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_MODE_IN                 BIT(16)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_OFFSET_CAL              BIT(15)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_SHORT_WR                BIT(14)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_SHORT_IN                BIT(13)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_GAIN_CAL                BIT(12)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_SKEW_CAL                BIT(11)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_SKEW_WR                 BIT(10)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_SKEW_IN(x)              (((x) & 0xFF) << 2)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_DLL_CAL                 BIT(1)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_DLL_WR                  BIT(0)

/* REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL11 */

#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_DLL_IN(x)               (((x) & 0x3F) << 22)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_DLL_OS(x)               (((x) & 0x3F) << 16)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_DLL_RD                  BIT(15)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_LDO_REF(x)              (((x) & 0x7) << 12)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_LDO_CAL                 BIT(11)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_LDO_WR                  BIT(10)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_LDO_IN(x)               (((x) & 0xF) << 6)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_LDO_OS(x)               (((x) & 0xF) << 2)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_TEST_MUX(x)             (((x) & 0x3))

/* REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL12 */

#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_CAL_DONE                BIT(8)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_VCMI_S(x)               (((x) & 0x3) << 6)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_BUF_VCMI_S(x)           (((x) & 0x3) << 4)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_BUF_VCMO_S(x)           (((x) & 0x3) << 2)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_BUF_CUR_S(x)            (((x) & 0x3))

/* REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL13 */

#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_RESERVED(x)             (((x) & 0xFFFFFFFF))

/* REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL14 */

#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_RESERVED(x)                 (((x) & 0xFFFF))

/* REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL15 */

#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_APLL_RESERVED(x)            (((x) & 0x1FFFFF))

/* REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_CTRL16 */

#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_DLL_LDO_CAL_DONE        BIT(10)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_DLL_OUT(x)              (((x) & 0x3F) << 4)
#define BIT_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_WCNADDA_SAR_LDO_OUT(x)              (((x) & 0xF))

/* REG_ANLG_PHY_G0_ANALOG_WCN_ADDA_TOP_REG_SEL_CFG_0 */

#define BIT_ANLG_PHY_G0_DBG_SEL_ANALOG_WCN_ADDA_TOP_WCNADDA_26MHZ_BUF_PD        BIT(0)


#endif /* ANLG_PHY_G0_H */


